1. Field of the Invention
This invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and other high speed IC's. The invention provides ultra low dielectric constant (low-k) interconnect structures having enhanced circuit speed, precise values of conductor resistance, and improved mechanical integrity. The structures of this invention have improved toughness and adhesion along with improved control over the metal line resistance compared to conventional structures. The present invention also provides many additional advantages which shall become apparent as described below.
2. Background Art
This application is related to application Ser. No. 09/795,431, entitled Low-k Dielectric Interconnect Structure Comprised of a Multi Layer of Spin-On Porous Dielectrics, assigned to the same assignee as the present application, and filed on Feb. 28, 2001, the contents of which are incorporated herein by reference.
Many low-k dielectric plus copper interconnect structures of the dual damascene type are known. For example, reference is made to U.S. Pat. No. 6,383,920, which is assigned to the same assignee as the present invention, and is incorporated in its entirety by reference, as if fully set forth herein. However, in order to achieve the necessary reduction in the RC delay in the future generations, porous materials must be used as the dielectric. In addition, due to the 5-20 nanometer pore sizes of porous organic materials, a buried etch stop layer is necessary to give smooth metal line bottoms. These structures undergo several processing steps including chemical mechanical polishing (CMP) of the copper, which create stresses within the dielectric stack that can lead to delamination. Delamination can occur due to poor adhesion at the etch stop to dielectric interfaces, or within the dielectric due to decreased toughness of the porous dielectric and increased stress near the interfaces.